As is well known, a prominent feature of electronic non-volatile memory devices, e.g., last-generation flash memory devices, is that a control logic circuit portion is incorporated in them to form an integral part the device. The control logic is not of inconsiderable complexity and importance being, as it is, requisite for executing program and erase algorithms.
The control logic circuit portion may be provided in different forms, such as any of those listed here below.
1. A wired logic, wherein the sequence of the functions to be performed is implemented by a network purely of logic gates. Understandably, in the event of modifications occurring in the instruction flow as a result of design alterations or changed technological requirements, the logic circuit portion must be entirely redesigned.
2. A finite state machine, consisting essentially of either a Moore's or a Mealey's machine the combinational portion whereof is provided by a PLA (Programmable Logic Array) logic structure. In the event of modifications being made, it suffices that the PLA logic structure be reprogrammed, for example by changing a limited number of masks, to implement a new function. In this case, the overall circuit design would be retained, to the benefit of modification and simulation times and cost of the operation.
3. A microprogrammed unit, which contains an instruction algorithm in a memory array. The instructions are carried out by a sequencer which is identical with those provided in microcontrollers and microprocessors. The algorithm-storing memory array may be any non-volatile memory, e.g., a ROM, in which case reprogramming will entail modifications to some masks, a PROM, EPROM, EEPROM, or flash-type memory, in which case reprogramming may be software based.
Additionally to executing user's algorithms, the control logic is used:                at the characterizing stage, to check all the logic and analog parts for full operability by emulating the user-mode operation to be, or measuring such characteristic parameters as the value attained by voltage boosters, if provided, or the value of the internally generated reference voltage.        at the EWS (Electrical Wafer Test) or final test stage, to perform all those operations that will make the memory ready for use by the ultimate customer, such as reference cell writing, setting up special UPROM or OTP registers, etc.        
It will be appreciated from the foregoing that the control logic circuit portion exacts careful designing, not only on account of its complex structure but also, and above all, of the need to have the operability of its many functions thoroughly checked. Incomplete coverage of all its operational aspects, and consequent circuit malfunctions, would require corrective actions which are specific to the type of the implementation used.
Wired logic-based approaches apparently admit of no corrective action.
Approaches based on a finite-state machine or a microprogrammed unit do admit of reprogramming, with greater or lesser degrees of difficulty. In all cases, however, the memory device must be tested before full operability of the control logic can be ascertained.
To test the control logic for its operability, techniques known as DFT (Design For Testability) are usually resorted to. These techniques consist of using special sequences or chains of storage components, e.g., latches and/or flip-flops, having a load input and an output for cascade connection to the next component in the chain. In the test mode, these “test chains” are loaded with predetermined data sequences as if they were single serial registers. Briefly, the control logic incorporates a hardware portion specially for performing test operations.
In response to forcing said data sequence, the control logic provides something of a “reaction to stimulus”, and a record of the data sequences and their responses, when compared with expected results provided by a simulation, will allow conformity of the circuit with the specifications to be verified and guaranteed. A drawback with the above testing method is that complex gates must be included in the design of the control logic portion devoted to testing, which expands the area requirements of the device to a considerable extent.
A commonly adopted solution consists of testing only the analog circuitry, and is followed by characterization. Where the operability of the various parts of the control logic are to be tested in situations other than those provided for by the algorithm, a certain number of test registers are included which are effective to drive the analog circuits, once suitably loaded. Again, the overall area for occupation by the circuit must be expanded, merely to enable the testing operations to be performed.
The technical problem underlying this invention is to provide a method of testing integrated memory devices with features appropriate to allow plural testing operations to be carried out, while avoiding the need for the circuit under test to incorporate dedicated circuit portions merely to enable such operations to be performed.